a片在线观看免费看视频_欧美婬片在线a_同性男男无遮挡无码视频_久久99狠狠色精品一区_《性妲己》电影在线观看_久久久99婷婷久久久久久_亚洲精品久久久久58_激情在线成人福利小电影_色婷婷久久综合五月激情网

0 賣盤信息
BOM詢價
您現在的位置: 首頁 > 品牌信息 > QUICKLOGIC

關于QUICKLOGIC

QUICKLOGIC

快輯半導體公司是一家無晶圓廠半導體公司,致力于開發低功耗,多核半導體平臺以及用于人工智能(AI),語音和傳感器處理的知識產權(IP)。 這些解決方案包括用于硬件加速和預處理的嵌入式FPGA IP(eFPGA),以及將eFPGA與其他處理器和外圍設備集成在一起的異構多核SoC。 快輯半導體最近收購的全資子公司SensiML Corporation的Analytics Toolkit通過使用AI技術的精確傳感器算法完善了端到端解決方案。 全方位的平臺,軟件工具和eFPGA IP支持在移動,可穿戴,可聽,消費,工業,邊緣和端點IoT上切實有效地采用AI,語音和傳感器處理。
為您找到相關結果 775 59 /26
QL4036-0PQ208I
型號:
QL4036-0PQ208I
品牌:
QUICKLOGIC
產品分類:
集成電路
描述:
ARCHITECTURE OVERVIEW The QuickRAM family of ESPs (Embedded Standard Products) offers FPGA logic in combination with Dual Port SRAM modules. The QL4036 is a 36,000 usable PLD gate member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35mm four-layer metal process using QuickLogic’s patented ViaLinkTM technology to provide a unique combination of high? performance, high density, low cost, and extreme ease-of-use. The QL4036 contains 672 logic cells and 14 dual port RAM modules(see Figure 1). Each RAM?module has 1,152 RAM bits, for a total of 16,128 bits. RAM Modules are Dual Port (one read port, one write port) and can be configured into one of four modes: 64(deep) x18 (wide), 128x9, 256x4, or 512x2 (see Figure 2). With a maximum of 204 I/Os, the QL4036 is available in 144-pin TQFP, 208-pin PQFP and 256-pin PBGA packages. DEVICE HIGHLIGHTS High Performance & High Density ■36,000 Usable PLD Gates with 204 I/Os ■300 MHz 16-bit Counters, 400 MHz Datapaths, 160+ MHz FIFOs ■0.35μm four-layer metal non-volatile CMOS process for smallest die sizes High Speed?Embedded SRAM ■14 dual-port RAM modules, organized in user-config urable 1,152 bit blocks ■5ns access times, each port independently accessible ■Fast and effecient for FIFO, RAM, and ROM functions Easy to Use / Fast Development Cycles ■100% routable with 100% utilization and complete pin-out stability ■Variable-grain logic cells provide high performance and 100% utilization ■Comprehensive design tools include high quality Verilog/VHDL synthesis Advanced I/O Capabilities ■Interfaces with both 3.3V and 5.0V devices ■PCI compliant with 3.3V and 5.0V busses for -1/-2/-3/-4 speed grades ■Full JTAG boundary scan ■Registered I/O cells with individually controlled clocks and output enables
拍明芯城微信圖標

各大手機應用商城搜索“拍明芯城”

下載客戶端,隨時隨地買賣元器件!

拍明芯城公眾號
拍明芯城抖音
拍明芯城b站
拍明芯城頭條
拍明芯城微博
拍明芯城視頻號